if (ridx >= sof) {
/* read of out-of-frame register returns an undefined value; 0 in our case. */
DPRINT("ignoring read from r%lu; only %lu registers are allocated!\n", r1, sof);
- panic("wrong stack register number (iip=%p)\n", regs->cr_iip);
+ panic("wrong stack register number (iip=%lx)\n", regs->cr_iip);
}
if (ridx < sor)
vcpu_get_rr(vcpu, reg, &oldrr.rrval);
newrr.rrval=val;
if (newrr.rid >= (1 << vcpu->domain->arch.rid_bits))
- panic_domain (NULL, "use of invalid rid %lx\n", newrr.rid);
+ panic_domain (NULL, "use of invalid rid %x\n", newrr.rid);
if(oldrr.ps!=newrr.ps){
thash_purge_all(vcpu);
}
vcpu_get_rr(current, va, &vrr.rrval);
if (vrr.ps != ps) {
// machine_tlb_insert(hcb->vcpu, entry);
- panic_domain(NULL, "not preferred ps with va: 0x%lx vrr.ps=%d ps=%d\n",
- va, vrr.ps, ps);
- return;
+ panic_domain(NULL, "not preferred ps with va: 0x%lx vrr.ps=%d ps=%ld\n",
+ va, vrr.ps, ps);
+ return;
}
hash_table = vsa_thash(hcb->pta, va, vrr.rrval, &tag);
if( INVALID_TLB(hash_table) ) {
}
vector &= ~0xf;
if (vector != IA64_DATA_TLB_VECTOR &&
- vector != IA64_ALT_DATA_TLB_VECTOR &&
- vector != IA64_VHPT_TRANS_VECTOR) {
-panic_domain(regs,"psr.ic off, delivering fault=%lx,ipsr=%p,iip=%p,ifa=%p,isr=%p,PSCB.iip=%p\n",
- vector,regs->cr_ipsr,regs->cr_iip,PSCB(v,ifa),isr,PSCB(v,iip));
+ vector != IA64_ALT_DATA_TLB_VECTOR &&
+ vector != IA64_VHPT_TRANS_VECTOR) {
+ panic_domain(regs,"psr.ic off, delivering fault=%lx,ipsr=%lx,iip=%lx,ifa=%lx,isr=%lx,PSCB.iip=%lx\n",
+ vector,regs->cr_ipsr,regs->cr_iip,PSCB(v,ifa),isr,PSCB(v,iip));
}
}
struct pt_regs *regs = (struct pt_regs *) &stack;
unsigned long code;
char buf[128];
- static const char * const reason[] = {
+ static const char *reason[] = {
"IA-64 Illegal Operation fault",
"IA-64 Privileged Operation fault",
"IA-64 Privileged Register fault",